The present invention relates to a semiconductor device package, in particular to a wiring substrate to be used for a package of a semiconductor device of a BGA (Ball Grid Array) type, and a semiconductor device employing such a wiring substrate.
As shown in FIG. 8(a) and FIG. 8(b), in a conventional resin sealed type semiconductor device of a BGA type employing a bonding wire, a semiconductor chip 71 is provided, with its circuit portion facing above, on a substrate 73 on which a wiring pattern 72 is provided on the side where the semiconductor chip 71 is mounted. Also, a metal thin wire connection electrode pad 74, which is an electrode terminal to be connected to the semiconductor chip 71 and which is provided at an end of each wiring of the wiring pattern 72, is connected to an output terminal 71a of the semiconductor chip 71 by a metal wire 75 (thin wire). Thus, the wiring pattern 72 on the substrate 73 and the semiconductor chip 71 are electrically conducted, and thereafter sealing is made so that the semiconductor chip 71, wiring pattern 72, and wire 75, etc., are coated with resin.
The resin sealed type semiconductor device includes a solder ball 76 (external terminal) which is provided on the other side of the resin sealed surface of the substrate 73. The solder ball 76 constitutes a signal terminal for electrically connecting each wiring of the wiring pattern 72 to an external circuit via a perforation 73a (external terminal mounting perforation) provided through the substrate 73. The resin sealed type semiconductor device is made into a final product by being cut into individual pieces of an external size (package size) of the resin sealed type semiconductor device per semiconductor chip 71.
Some of such resin sealed type semiconductor devices adopt a wiring substrate in which wiring pattern 72 is made of a metal of a single layer. In this kind of resin sealed type semiconductor device, in the case where the number of external terminals, i.e., the number of signal terminals which need to be externally connected, is large and the semiconductor chip 71 is small as compared with the package size, the distance from the semiconductor chip 71 to the metal thin wire connection electrode pad 74 on the substrate 73 becomes long. As a result, there is a tendency that the length of the wire 75 for connecting the semiconductor chip 71 and the metal thin wire connection electrode pad 74 is increased. This tendency becomes more prominent when the external size of the resin sealed type semiconductor device is increased due to the increased number of external terminals, for example, by an increase in number of signal terminals, and/or when the size of the semiconductor chip 71 (semiconductor chip size) is reduced while the number of signal terminals remains unchanged.
Further, as the length of wire 75 is increased by the increased difference in size between the external size of the resin sealed type semiconductor device and the semiconductor chip 71, the angle of wire 75 with respect to the semiconductor chip 71 (wire angle) becomes smaller, and the intervals between the wires 75 are reduced. Thus, such a resin sealed type semiconductor device poses the problem that the wires 75 are susceptible to coming into contact with each other in a resin sealing step after wire bonding.
As described, the number of external terminals comprises the biggest factor in determining the external size of the resin sealed type semiconductor device, and also causes the wire contact between wires 75 as induced by the difference in size between the external size of the resin sealed type semiconductor device and the semiconductor chip 71. Other factors which determine the external size of the resin sealed type semiconductor device include, for example, the number of metal thin wire connection electrode pads.
When the metal thin wire connection electrode pads 74 are to be aligned in a single row as shown in FIG. 8(a) in a large number, the metal thin wire connection electrode pads 74 cannot be confined within the external size of the resin sealed type semiconductor device, and it is required as a result to position the metal thin wire connection electrode pads 74 outside of the external size of the resin sealed type semiconductor device. In such a case, the external size itself of the resin sealed type semiconductor device needs to be made large and the problem of wire contact between wires 75 is induced.
Meanwhile, in order to align all the metal thin wire connection electrode pads 74 within a desired external size of the resin sealed type semiconductor device, the metal thin wire connection electrode pads 74 may be aligned in plural rows, e.g., in two rows, by shifting the positions of metal thin wire connection electrode pads 74 of adjacent wiring. However, with this method, the pitch of the metal thin wire connection electrode pads 74 becomes small, and causes the problem of wire contact between the wires 75 to occur in the vicinity of the metal thin wire connection electrode pads 74, and also causes wire bonding tools to come into contact with each other, and thus this method still does not solve the problem of wire contact between wires 75 in the resin sealing step after connecting wires 75. In particular, when the wire angle is small between the semiconductor chip 71 and the position of the metal thin wire connection electrode pads 74 on the substrate 73, the distance between the wires 75 is further reduced, and the danger of contact between wires 75 and between wire bonding tools is increased.
Further, when the number of external terminals (signal terminals) is large and the pitch between external terminals is small, by various limitations such as, for example, wire length and wire angle, it may be necessary to provide the metal thin wire connection electrode pads 74 at a position from which wire bonding cannot be made directly from the semiconductor chip 71. In such a case, the external terminals which are connected to such metal thin wire connection electrode pads 74 cannot be used as the signal terminals.
As described, the problem of wire contact, which often occurs when the semiconductor chip size is relatively smaller than the package size and when the number of metal thin wire connection electrode pads is large, is inflicted by wire length and wire angle.
A wiring pattern having a large number of metal thin wire connection electrode pads is disclosed, for example, in Japanese Unexamined Utility Model No. 84460/1989 (Jitsukaihei 1-84460) (published date: Jun. 5, 1989), in which plural kinds of semiconductor chips having different configurations are aligned and mounted on the same single substrate without any change in the wiring pattern. As shown in FIG. 9, the wiring pattern is provided such that on a substrate 84 mounting semiconductor chips 81, 82, and 83 (chip parts), plural lines L1 to Ln are formed, and the lines L1 to Ln are provided, at an end of each line, with a plurality of metal thin wire connection electrode pads P1 to Pn and Q1 to Qn (bonding pads) which are to be used for wire bonding with the output terminals 81a, 82a, and 83a of the semiconductor chips 81, 82, and 83, respectively, by which the lines L1 to Ln extend toward a heat generating body via the metal thin wire connection electrode pads Q1 to Qn from the metal thin wire connection electrode pads P1 to Pn as a starting point.
Thus, in the above wiring pattern, wire bonding is made in accordance with the shapes of the semiconductor chips 81, 82, and 83 so that, for example, with respect to the semiconductor chip 81, the output terminals 81a of the semiconductor chip 81 and the exposed metal thin wire connection electrode pads P1 and P3, P2mxe2x88x921, P2, P4, and P2m on the first two rows are connected to each other by wire bonding, and with respect to the semiconductor chip 82 which is larger than the semiconductor chip 81, the semiconductor chip 82 is mounted on top of the metal thin wire connection electrode pads of the first two rows, and the output terminals 82a of the semiconductor chip 82 are connected to the metal thin wire connection electrode pads Q2axe2x88x921, Q2a+1, Q2a, and Q2a+2 on the last two rows, thus adding a degree of freedom in bonding position between the output terminals 81a, 82a, and 83a of the semiconductor chips 81, 82, and 83 and the metal thin wire connection electrode pads P1 to Pn and Q1 to Qn, and allowing optimum metal thin wire connection electrode pads to be selected for the semiconductor chips 81, 82, and 83 having a difference size.
Further, in the above wiring pattern, by selecting optimum metal thin wire connection electrode pads P1 to Pn and Q1 to Qn for each of the semiconductor chips 81, 82, and 83 having a different size, the length of the wire connecting the output terminals 81a, 82a, and 83a of the semiconductor chips 81, 82, and 83 and the metal thin wire connection electrode pads P1 to Pn and Q1 to Qn of the wiring pattern can be reduced.
Meanwhile, in order to be compatible with the multi-pins of highly integrated semiconductor chips and to eliminate the limitation imposed by the wire length, Japanese Unexamined Patent Publication No. 24929/1992 (Tokukaihei 4-24929) (published date: Jan. 28, 1992) discloses a ceramic package as shown in FIG. 10, in which a relay circuit pattern 94 having a relay substrate 95 on its upper surface is provided between a bonding portion (metal thin wire connection electrode pad) 91a of a circuit pattern 91 which is to be connected to external leads and a mount region of a semiconductor chip 92, where one end of the relay circuit pattern 94 is connected to an output terminal 92a of the semiconductor chip 92 by a bonding wire 93 and the other end is connected to the bonding portion 91a of the circuit pattern 91 by the bonding wire 93.
In this ceramic package, the semiconductor chip 92 and the circuit pattern 91 are connected to each other via the relay circuit pattern 94 which is provided on the relay substrate 95 between the semiconductor chip 92 and the circuit pattern 91, and for this reason as compared with the case where the semiconductor chip 92 and the circuit pattern 91 are connected to each other by direct wire bonding, the length of wire 93 can be reduced, thus making the device compatible with the multi-pins.
However, in the package of the resin sealed type semiconductor device of a BGA type, as shown in FIG. 8(a) and FIG. 8(b), on the wiring pattern 72 is provided a land pattern (a group of lands 72a) composed of lands 72a covering the external terminal mounting perforations 73a. 
Thus, when the arrangement of Japanese Unexamined Utility Model No. 84460/1989 (Jitsukaihei 1-84460), in which rows of plural metal thin wire connection electrode pads are formed at an end of each wiring is applied to the wiring pattern 72 of the wiring substrate used in the resin sealed type semiconductor device of a BGA type as shown in FIG. 8(a) and FIG. 8(b), the rows of metal thin wire connection electrode pads 74 are provided separately from the land pattern (a group of lands 72a). As a result, the area on the substrate other than the area where the land pattern is formed cannot be used efficiently, and the package size is increased.
Further, the ceramic package as disclosed in Japanese Unexamined Patent Publication No. 24929/1992 (Tokukaihei 4-24929) requires the special relay substrate 95 for relaying the bonding wires 93 as shown in FIG. 10, and the number of manufacturing steps and costs are increased.
It is an object of the present invention to inexpensively provide a wiring substrate and a semiconductor device with a good yield, which are capable of reducing wire length and preventing wire contact even when a semiconductor chip is smaller than a package size.
In order to achieve the above object, a wiring substrate of the present invention includes a wiring pattern provided per each wiring with a land covering a perforation for mounting an external terminal, the land being provided on a side of the wiring pattern on which side a semiconductor chip is mounted,
wherein a plurality of electrode terminals (e.g., metal thin wire connection electrode pads having a quadrilateral or pentagonal shape) for electrically connecting the wiring and the semiconductor chip by wire bonding are provided per each wiring, and at least one of the plurality of electrode terminals is provided between lands.
With this arrangement, by the provision of the plurality of electrode terminals per each wiring, the electrode terminals for electrically connecting each wiring and the semiconductor chip can be flexibly changed. Further, by the provision of the electrode terminals between lands, the number of electrode terminals can be increased without causing increase in external size (package size) of the semiconductor device, and also the layout of wiring where wires are likely to contact with each other in wire bonding can be easily changed, and the trouble such as wire contact between wires can be prevented.
Thus, with the above arrangement, even when the number of, for example, external terminals is large and the semiconductor chip is smaller than the external size (package size) of the semiconductor device, the wires are prevented from coming into contact with each other in wire bonding between the semiconductor chip and each wiring provided on the wiring substrate. Further, with the above arrangement, it is not required to provide a special relay substrate, etc., in addition to the wiring pattern, thus realizing an inexpensive arrangement. As a result, it is possible to provide a wiring substrate which can realize an inexpensive semiconductor device which can be manufactured with a good yield.
In order to achieve the foregoing object, another wiring substrate of the present invention includes a wiring pattern provided per each wiring with a land covering a perforation for mounting an external terminal, the land being provided on a side of the wiring pattern on which side a semiconductor chip is mounted, wherein electrode terminals for electrically connecting the wiring and the semiconductor chip by wire bonding are provided between lands, and relay wiring (e.g., wiring having relaying metal thin wire connecting pads at the both ends) for electrically connecting the electrode terminals and the semiconductor chip by wire bonding is provided between the wiring pattern and a semiconductor mounting region.
With this arrangement, even when the number of, for example, external terminals is large and the semiconductor chip is considerably smaller than the external size (package size) of the semiconductor device, or in the case where the external terminal pitch is narrow and there is no degree of freedom in positioning of the electrode terminals, or even when all wiring patterns are to be made of a metal of a single layer, the length of the wire used for wire bonding of the semiconductor chip and each wiring can be made shorter, thus preventing wire contact. Thus, with the above arrangement, it is possible to provide a wiring substrate which can realize an inexpensive semiconductor device which can be manufactured with a good yield.
In order to achieve the foregoing object, a semiconductor device of the present invention includes the above wiring substrate.
With this arrangement, because the semiconductor device includes the wiring substrate, even when the semiconductor chip is smaller than the package size, the wire length can be reduced, and it is possible to inexpensively provide a semiconductor device with a good yield, in which no wire contact occurs.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.